Electron beam deflection circuit

ABSTRACT

A vertical deflection circuit which has an output stage formed in the type of single-ended push-pull amplifier and a voltage supplying circuit with a charge storing device connected between a voltage source and the output stage. The voltage supplying circuit supplies a voltage from the voltage source to the output stage and simultaneously charges the charge storing device during a retrace period and also supplies a voltage lower than the voltage of the voltage source to the output stage by discharging of the charge storing device during a trace period.

United States Patent [191 Morio et al.

[451 Nov. 18, 1975 ELECTRON BEAM DEFLECTION CIRCUIT Inventors: MinoruMorio, Kamakura; Yutaka Nakagawa, Tokyo, both of Japan Assignee: SonyCorporation, Tokyo, Japan Filed: Jan. 11, 1974 Appl. No.: 432,609

Foreign Application Priority Data Jan. 19, 1973 Japan 48-8817(U] US. Cl.315/396 Int. Cl. H01J 29/72 Field of Search 315/396, 397, 403, 406,

References Cited UNITED STATES PATENTS 4/1969 Nix et al. 315/3973,784,857 l/l974 Christopher 315/396 Primary ExaminerT. H. TubbesingAttorney, Agent, or Firm-Hill, Gross, Simpson, Van Santen, Steadman,Chiara & Simpson ABSIRACT A vertical deflection circuit which has anoutput stage formed in the type of single-ended push-pull amplifier anda voltage supplying circuit with a charge storing device connectedbetween a voltage source and the output stage. The voltage supplyingcircuit supplies a voltage from the voltage source to the output stageand simultaneously charges the charge storing device during a retraceperiod and also supplies a voltage lower than the voltage of the voltagesource to the output stage by discharging of the charge storing deviceduring a trace period.

8 Claims, 15 Drawing Figures U.S. Patent Nov. 18, 1975 Sheet 2 of43,921,036

U.S; Patent Nov. 18, 1975 Sheet3of4 3,921,036

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U.S. Patent Nov. 18, 1975 ELECTRON BEAM DEFLECTION CIRCUIT BACKGROUND OFTHE INVENTION 1. Field of the Invention This invention relates generallyto deflection circuits for deflecting electron beams, and moreparticularly to an improvement in vertical deflection circuits having anoutput stage formed in a single-ended push-pull amplifier.

I 2. Description of the Prior Art In television receivers and the likewhich have a cathode 'ray image reproducing device, vertical andhoridevice to achieve field and line scannings of the electron beams.Various kinds of circuits have previously been proposed as verticaldeflection circuits and one of these vertical deflection circuits is atransistorized cir- ,cuit having an output stage, which supplies asawtooth -wave current to a vertical deflection winding, formed in atype of single-ended push-pull amplifier. Such a transistorized circuithas been often employed because of its advantage of increasedefficiency. However, previously proposed vertical deflection circuitshaving the output stage of single-ended push-pull amplifier type wereunable to avoid expending a certain amount of uselesspower consumptionwhich is essentially caused by their circuit construction, and thereforethe effi- .ciency, namely, the ratio between an output power at thevertical deflection winding and the power supplied to the circuit is notincreased. Some improved circuits of such a type have also been proposedto diminish the above mentioned useless power consumption, but with suchcircuits, none seem to have obtained satisfactory 1 results.

OBJECTS AND SUMMARY OF THE INVENTION An object of the present inventionis to provide an improved vertical deflection circuit having an outputstage of the single-ended push-pull amplifier type..'

Another object of the present invention is to provide a verticaldeflection circuit having an output stageof the singleended push-pullamplifier type which is improved to operate with increased efficiency.

The present invention provides a novel vertical deflection circuithaving an outputstage of the singleended push-pull amplifier type whichoperates from a first operation voltage supplied from a voltage sourceduring a retrace period and from a' second operation voltage lower thanthe first voltage'during a trace per- BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a schematic circuit diagram showing a prior art deflectioncircuit with an output stage of a singleended push-pull amplifier typ'e;

FIGS. 2A to 2C are schematic waveform diagrams used for explanation ofthe operation of the circuit shown in FIG. 1;

zontal deflection circuits are employed for deflecting electron beams inthe cathode ray image reproducing FIG. 3 is a schematic circuit diagramshowing one embodiment of deflection circuits according to the presentinvention; 7

FIGS. 4A to 4F are schematic waveform diagrams used for explanation ofthe operation of the embodiment of the present invention shown in FIG.3;

FIG. 5 is a schematic circuit diagram showing a part of a modificationof the embodiment of the present invention shown in FIG. 3.

FIGS. 6 and 7 are schematic circuit diagrams showing other embodimentsof deflection circuits according to the present invention; and

FIG. 8 is a schematic waveform diagram used for explanation of theoperation of the embodiment of the present invention shown in FIG. 7.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Inorder to facilitate a betterunderstanding of the present invention, an example of the prior artdeflection circuit with an output stage of the single-ended push-pullamplifier type will be now described with reference to FIGS. 1 and 2.

FIG. 1 shows a part of the prior art vertical deflection circuit with anoutput stage formed in a single-ended push-pull amplifier. In thefigure, reference numeral 1 designates a singleended push-pull amplifiercircuit with a pair of transistors Q and 0 forming an output stage. Adriving signal S of sawtooth wave, which is in synchronism with thevertical period, is supplied to an input terminal 2 whichis provided atthe base electrodes of the transistors Q and O to switch both thetransistors. Thus, through a deflection yoke L which is connectedthrough a capacitor C to a connection point 1 between the emitterelectrodes of the transistors Q and Q a sawtooth wave signal (ofcurrent) is generated, as is well known.

With such a prior art vertical deflection circuit, if the emittervoltage at the connection point 1 is taken in consideration, it is apulse like waveform during a retrace period Tr but a voltage waveformwhich changes to decrease linearly during a trace period Ts as shown byS in FIG. 2A, which is obtained at every single field interval. In thiscase, the maximum signal output voltage E obtained at the emitterelectrode of the transistor Q is somewhat lower than a power sourcevoltage E which is applied to a terminal 3 connected to the collectorelectrode to the transistor Q due to the circuit construction, thesaturation voltage of transistor Q and for other possible reasons.Further, since the sawtooth wave driving signal S shown in FIG. 2C isapplied to the base electrode of the transistor 0,, the transistor Q ismade conductive during the time period between times t, and Accordingly,if the electric power consumed in the transistor O is taken in account,its voltage component is shown by a trapezoid area as crosshatched inFIG. 2A. While the current flowing through the transistor Q at this timeis B times the driving signal 5 where B is the current gain of thetransistor Q the current component of the power consumed in transistor Qis shown as a current 8:, which is approximately the same as the drivingsignal S, in waveform, as shown in FIG. 28 by the cross-hatch. As aresult, the power consumption P in transistor Q, is the product of thevoltage component shown in FIG. 2A by the crosshatch and the currentcomponent is shown in FIG. 2B by the cross-hatch.

Now, from the operation point of view, the transistor Q is madeconductive between the times and t;; as shown in FIGS. 2A to 2C.However, the voltage portion surrounded by the dotted line in FIG. 2Adoes not appear at the emitter electrode of transistor Q but is appliedacross the emitter-collector electrodes of transistor Q which abovevoltage portion is a useless voltage. Thus, the power consumption due tothis useless voltage in the transistor Q is a useless power consumptionand hence the output efficiency of the above prior art verticaldeflection circuit is lowered.

As mentioned above, the present invention has as an object a circuitarrangement which will avoid the lowering of output efficiency caused inthe prior art vertical deflection circuit and which will increase theoutput efficiency, and will propose a vertical deflection circuit smallin power consumption and simple in circuit construction.

A preferred embodiment of a vertical deflection circuit according to thepresent invention will be now described with reference to FIG. 3.

In the embodiment of FIG. 3, a single-ended pushpull amplifier circuitis shown, which forms an output stage 31, and which consists of a pairof transistors Q and Q Since the transistors Q and Q are complementaryin this embodiment, a common input terminal 32 is provided at the baseelectrodes of both of the transistors Q and Q A driving signal S havinga sawtooth waveform is applied to the input terminal 32 to make thetransistors Q11 and Q Conductive and non-conductive, alternately. To aconnection point I between the emitter electrodes of both thetransistors O and Q there is connected in series a deflection yoke L anda capacitor C. Thus, a deflection current with a sawtooth waveform flowsthrough the deflection yoke L, which is substantially the same as in theprior art. To a voltage source terminal 33 through a path m, there isconnected a control element or switching device ll such as a gatecontrolled switch (GCS) transistor, silicon controlled rectifier (SCR),or the like in series so as to intermittently supply a voltage E, fromthe voltage source to the output stage 31. The control electrode of theswitching device 11 is connected to the connection point I through adifferentiating RC circuit 12, if necessary, so as to be supplied with apulse voltage generated at the deflection yoke L and hence to becontrolled in conduction by the pulse voltage. In the illustratedembodiment, the GCS is employed as the switching device or controlelement 11.

Between the cathode electrode of GCS 11 and the collector electrode oftransistor Q there is connected an operation voltage generating circuit13 so as to determine the operating voltage for the output stage 31 ofthe single-ended push-pull amplifier type during the trace period Ts.The operation voltage generating circuit 13 serves to establish avoltage (l/n)E,, (n being a positive integer), from the voltage E of thevoltage source. For this purpose, the operation voltage generatingcircuit 13 may be formed ofa plurality of capacitors 14a, 14b, connectedin series or parallel with one another. In the illustrated embodiment,the operation voltage is selected, as %E,,, so that only two capacitors14a and 14b are used. In the circuit 13, diodes 15a and 15b are employedfor blocking the reverse current. A diode 15c is connected to one end ofthe capacitor 14a and a lead wire L,, which is connected in parallel tothe series connection of capacitor 14a and diodes 15a and 15b, to form adischarge path for the capacitor 14a.

A terminal 17, which is connected to the cathode electrode of the diode15b through a diode 16, is a terminal to which a voltage Es is supplied.The voltage Es is selected lower than the voltage E to cause the diode16 to be in reverse biased condition during the operation of thevertical deflection circuit and hence in the nonconductive state withthe result that the terminal 17 is disconnected from the output stage 31and the circuit 13 to have no effect on the deflection operation. A coil18, connected to the anode of the GCS 11, is used to make the chargingtime constant of capacitors 14a and 14b long during the conductive stateof GCS 11. In FIG. 3, reference numerals 20a and 20b indicate terminalsof circuit 13.

The operation of the circuit shown in FIG. 3 will be now described withreference to FIGS. 4A to 4F.

When the driving signal 5, shown in FIG. 4A is supplied to the terminal32, the transistor Q1 is made conductive during the positive interval ofdriving signal S and the transistor Q is made conductive during thenegative interval of driving signal 3,. Upon the motive condition of thedeflection circuit, the GCS 11 is nonconductive. For example, if themotive voltage Es is supplied to the terminal 17 at a time t since thetransistor Q1 is Conductive, a current S in accordance with the drivingsignal S as shown in FIG. 4B, flows through the circuit of transistor Q-deflection yoke L- capacitor C and the capacitor C is charged by thiscurrent. As the driving signal 8,, becomes negative at a time t thetransistor Q becomes nonconductive but the transistor Q is madeconductive. As a result, the charge stored in the capacitor C isdischarged through the circuit of transistor Q and hence a current 5,,shown in FIG. 3C, flows through transistor Q and a current, which isreverse in polarity with respect to that flowing when the transistor Qis conductive (see arrow b in FIG. 3), flows through the deflection yokeL. This current is increased with time lapse.

At a time 1 the transistor Q12 is made nonconductive by the drivingsignal S but the transistor Q is made conductive again by the drivingsignal S and therefore the latter transistor will have the emittercurrent flow therethrough. However, at this time, reverse current flowsthrough the deflection yoke L, so that the transistor O is biasedreversely. Accordingly, the current flowing through the deflection yokeL flows to charge a stray capacitor C existing in parallel with thedeflection yoke L as shown by a dotted line in FIG. 3 and also flowsthrough the transistor Q reversely. Thus, the emitter voltage oftransistor Q increases abruptly to produce a pulse voltage which is aretrace pulse. The pulse width of the retrace pulse is determined by aresonance circuit formed of the deflection yoke L and the capacitorwhich is connected equivalently in parallel thereto and includes thestray capacitor C. That is, the retrace period Tr between the time and atime is determined. Since the pulse voltage is higher than the collectorvoltage of transistor Q the pulse voltage is applied through thedifferentiating circuit 12 to the gate electrode of the GCS 11 to makethe same conductive. Thus, the voltage E of the voltage source isapplied to the collector electrode of transistor Q to make its collectorvoltage E shown by S in FIG. 4E. The capacitors 14a and 14b areconnected in series to the terminal 33 through the GCS 11 and, as aresult, each of the capacitors 14a and 14b is charged up to a voltage'rE respectively, with the polarity as shown in FIG. 3. The retracepulse voltage rises to the voltage E 'when the emitter voltage oftransistor Q is lowered,

the emitter voltage of transistor Q becomes lower than itscollectorvoltage, and the 'gate voltage of GCS 11 becomes lower than its cathodevoltage with the result that the GCS 11 is made non-conductive andconsequently the voltage E is cut-off. A waveform S shown in FIG. 4Dindicates the current flowing through the GCS 11. Since the transistorQ1 is conductive during the time interval between the times 1 and a timet;,,

the voltages /E stored in the capacitors 14a and 14b respectively aredischarged through the loop of the capacitor 14a transistor Q deflectionyoke L capacitor C diode c capacitor 14a and the loop of the capacitor14b diode 15b transistor Q11 deflection yoke L capacitor C capacitor14b, respectively. In this case, the discharges of capacitors 14a and14b are parallel discharges so that a voltage supplied to the collectorelectrode of the transistor Q is not the voltage E, but the chargingvoltage to the capacitors 14a and 14b, namely, /E Thus, the collectorvoltage of the transistor Q has a waveform shown in FIG. 4E. During thetime interval from the time 1 to a time t at which the transistor Q imade conductive again, the transistor Q is conductive and theabove-mentioned discharging paths or loops are not formed with theresult that the collector voltage of transistor Q is held at an almostconstant value slightly lower than rE Even if the GCS 11 is madenonconductive and the supply of the voltage E of the voltage source isstopped as described above, the single-ended push-pull amplifier typecircuit of the output stage 31 is supplied with the operation voltagesignal of approximately 95B, and hence the voltage S at the emitterelectrode of the transistor O that is, at the connection point Idecreases gradually as shown in FIG. 4F due to the voltage drop causedby the current flowing through the resistor component of deflection yokeL or current S flowing through transistor Q In this case, if the powerconsumption P inthe transistor Q is taken into account, its voltagecomponent is substantially shown by a triangular portion by thecross-hatch in FIG. 4F. This voltage component corresponds to thetriangular portion of the cross-hatched voltage component of FIG. 2A,which is surrounded by the waveform S and the voltage E, between thetimes t and in FIG. 2A, in the prior art shown in FIG. 1. Accordingly,it will be easily understood that the power consumption P in thetransistor Q of the invention, which is obtained as the product of theabove consumed voltage component and the consumed current componentshown in FIG. 48 by the cross-hatch (corresponding to the cross-hatchedportion of FIG. 2B), is much reduced as compared with that of the priorart. In

other words, with the present invention, the useless voltage componentshown by a dotted line hatch in FIG. 4F, which corresponds to theuseless voltage component shown by the dotted line block in FIG. 2A ofthe prior art, is eliminated. As a result, with the present inventionthe total power consumption can be greatly reduced to improve the outputefficiency.

In the embodiment of FIG. 3, the operation voltage for the single-endedpush-pull amplifier type circuit 31 is made yE during the trace periodby the employment of two capacitors 14a and 14b in the operation voltagegenerating circuit 13. However, there is no need for the presentinvention to be limited to the embodiment of FIG. 3, but, by way ofexample, It number of capacitors are used to produce an operationvoltage of l/n)E,,, in the manner mentioned above. Further, it iseffective for narrowing the retrace period Tr without lowering theoutput efficiency that the operation voltage be made small as comparedwith the voltage E of the voltage source.

FIG. 5 is a circuit-diagram showing another embodiment of the operationvoltage generating circuit 13 in which three capacitors 14a, 14b and 14care used.

In the embodiment of FIG. 5, diodes 15b, 15c, lSe and 15fserve forforming the discharge path of the capacitors, and diodes 15a and 15dserve for blocking the reverse current. In this case, the voltage of%E,, is stored in each of capacitors 14a to 14c, respectively. Thedetailed description on this embodiment will be omitted because it maybe apparent to one skilled in the art.

FIG. 6 is a circuit diagram for showing another embodiment of thevertical deflection circuit according to the present invention in whichthe same reference numerals and symbols as those used in FIG. 3 indicatethe same elements.

In the embodiment of FIG. 6, the operation voltage generating circuit13, which supplies the operation voltage to the single-ended push-pullamplifier type circuit forming theoutput stage 31, is formed as follows.A series connection of a capacitor 21a, a diode 22a and a capacitor 21bis provided in parallel with the transistors Q11 and On, which form thesingle-ended push-pull amplifier type circuit. A diode 22b is connectedin parallel to the series connection of the diode 22a and capacitor 21b,and a diode 22c is connected in parallel to the series connection of thecapacitor 21a and diode 22a. The above connections are connected to theGCS 1 1 and the collector electrode of transistor Q11 through theterminals 20a and 20b, respectively.

In this embodiment, the diode 22a serves to form the charging path forthe capacitors 21a and 21b, while the diodes 22b and 220 serve to formthe discharging paths for charges stored in the capacitors 21a and 21b,respectively. The motive circuit shown in FIG. 3 is omitted in FIG. 6.

The operation of the embodiment shown in FIG. 6 will be now described.In this embodiment, the retrace pulse is generated at theconnectionpoint I and the GCS 11 is made conductive and nonconductive inaccordance with the retrace pulse, as in the case of the embodimentshown in FIG. 3. During the retrace period Tr or during the timeinterval in which the GCS 11 is conductive, the terminal 20a is suppliedwith the voltage E, of the voltage source from the terminal 33, andhence the output stage 31 is supplied with the voltage E through theterminal 20b and the capacitors 21a and 21b are charged with thepolarity shown in FIG. 6 and their terminal voltages become Erespectively. While, during the trace period Ts or the time interval inwhich the GCS 11 is made nonconductive, the voltage E is not supplied tothe terminal 20a, but the voltage rE stored in the capacitors 21a and21b is supplied to the output stage 31. That is, the charge stored inthe capacitor 21a is discharged through the closed path of the capacitor21a transistor Q deflection yoke L capacitor C diode 22b capacitor 21aand the charge stored in the capacitor 21b is discharged through theclosed path of the capacitor 21b diode 22c transistor Q deflection yokeL capacitor C capacitor 21b, respectively, to supply the voltage #515,,to the collector electrode of transistor Q through the terminal 20b. Asa result, it will be easily understood that the embodiment of FIG. 6achieves the deflection operation and improves the output efficiencylike the embodiment of FIG. 3. In this case, it is of course possiblethat n number of capacitors connected in series are used in the circuit13 to make the operation voltage of( l/n)E,, during the trace period.

FIG. 7 is a circuit diagram for showing a further embodiment of theinvention which uses (l/rz)E, (in the illustrated embodiment, rfiE asthe operation voltage during the trace period Ts and can make theoperation voltage during the retrace period Tr higher than the voltageE,,. In this embodiment, of course, only one voltage source is employed.

The operation voltage generating circuit 13 used in this embodiment isessentially identical to that used in the embodiment of FIG. 6, so thatits corresponding elements are shown with the corresponding numerals,and the reference numerals identical to those of FIG. 6 designate thesame elements.

In FIG. 7, reference numerals 25a and 25b represent diodes for blockingthe reverse current, and 25c is a diode for blocking the reverse currentalso. A capacitor 24 is connected in parallel to the series connectionof diodes 25a and 25b to superpose the charted voltage in the capacitor24 onto the voltage E of the voltage source during the retrace periodTr. That is, the voltage yE charged in the capacitors 21a and 21b duringthe retrace period Tr are discharged through the transistor Q during thetrace period Ts and also through the series connection of the capacitor24 and a resistor 23 so that the capacitor 24 is charged to %E,,. Thecharge stored in the capacitor 24 is discharged through the transistor Qduring the retrace period Tr, so that the operation voltage supplied tothe collector electrode of transistor Q during the retrace period Trapproximately becomes the voltage E, of the voltage source plus thecharged voltage 'rE in the capacitor 24 (i.e., E, %E 3/2 E The voltagewaveform at the connection point 1 is shown S, in FIG. 8. Thus, it willbe understood that the embodiment of FIG. 7 can improve the outputefficiency.

Further, in the embodiment of FIG. 7, the gate electrode of the GCS I1is supplied with the control voltage through a transformer 26, which isthe difference between the embodiments of FIGS. 6 and 7. The transformer26 has primary and secondary windings 26a annd 26b, the primary winding260 being connected across the deflection yoke L, while the secondarywinding 26b being connected between the gate and cathode electrodes ofthe GCS 11. In this case, it should be noted that the transformer 26 isonly an example of means for applying the control voltage to the gateelectrode of the GCS 11.

As described above, with the present invention, the output efficiency isgreatly improved with respect to the prior art with a simple circuitconstruction and with only one operation voltage source, andaccordingly, a superior vertical deflection operation can be attainedwith relatively small power consumption. Further, the

retrace period can be shortened without lowering the output efficiency.V

In the above embodiments of the present invention, the GCS is usedmainly as the switching element or device 11, but the other switchingelement such as a transistor or the like can be, of course, used, asmentioned previously, and the retrace pulse produced at the connectionpoint l is utilized as the signal for controlling the switching element11 but it is, of course, possible to use other signals which may changein accordance with the trace and retrace periods.

It may be apparent to those skilled in the art that many modificationsand variations could be effected without departing from the spirit andscope of the novel concepts of the present invention.

We claim as our invention:

1. A deflection circuit comprising:

a. an output circuit including a pair of transistors connected in asingle-ended push-pull amplifier array and a deflection coil connectedto the output end of said pair of transistors, said deflection coilbeing supplied with a deflection current in trace and retrace periods;

b. a voltage terminal provided to be connected to a voltage source;

0. switch means connected to said voltage terminal;

d. circuit means having charge storing means and connected between oneend of said output circuit and said switch, said circuit means supplyinga first voltage to said output circuit and simultaneously charging saidcharge storing means during the retrace period and supplying a secondvoltage lower than said flrst voltage to said output circuit by thedischarging of said charge storing means during the trace period; and

e. control means for controlling the conductivity of said switch meansin response to the turning of the period between the trace and retraceperiods.

2. A deflection circuit according to claim 1, wherein said circuit meanscomprises a voltage supplying path for supplying the voltage of saidvoltage source to said output circuit, plural capacitors, firstconnecting means for making a series connection of said pluralcapacitors connected to said voltage supplying path to charge the seriesconnnected plural capacitors by said voltage source during the retraceperiod and second connecting means for connecting each of said pluralcapacitors to said one end of said output circuit with respective pathsparallel to each other to make each of said capacitors discharge towardsaid output circuit during the trace period.

3. A deflection circuit according to claim 2, wherein said firstconnecting means includes at least one unidirectional element connectedbetween two of said plural capacitors, and said second connecting meansincludes plural additional unidirectional elements each connected toeach of said plural capacitors to make plural series paths connected tosaid one end of said output circuit in parallel to each other.

4. A deflection circuit according to claim 3, wherein said circuit meansfurther comprises an additional capacitor connected between said switchand said one end of said output circuit, an impedance element con nectedto a junction between one end of said additional capacitor and saidswitch, and a further additional unidirectional element provided in saidvoltage supplying path.

5. A deflection circuit according to claim 1, wherein said control meanscomprises means for supplying a control signal which varies inaccordance with the trace and retrace periods to said switch means so asto make said switch means nonconductive during the trace period andconductive during the retrace period.

6. A deflection circuit according to claim 5, wherein said control meansfurther comprises means for producing said control signal in response toa pulse ob- 10 tained at the output end of said couple of transistors.

7. A deflection circuit comprising:

a. an output circuit including a pair of transistors connected in asingle-ended push-pull amplifier array and a deflection coil connectedto the output [5 end of said pair of transistors, said deflection coilbeing supplied with a deflection current in trace and retrace periods; 7Y

b. a voltage terminal provided to be connected to avoltage source;

c. switch means with one end connected to said voltage terminal;

d. circuit means comprising a connecting path connecting the other endof said switch to one end of said output circuit, a series connection ofa first capacitor, a first diode and a second capacitor, one end of saidseries connection being connected to said connecting path, a seconddiode connected across the series connection of said first capacitor andsaid first diode and a third diode connected across the seriesconnection of said first diode and said second capacitor; and

e. control means for controlling the conductivity of said switch meansin response to the turning of the period between the trace and retraceperiods.

8. A deflection circuit according to claim 7, wherein said switch meanshas a control terminal and said control means is connected between saidoutput end of said pair of transistors and said control terminal.

1. A deflection circuit comprising: a. an output circuit including apair of transistors connected in a single-ended push-pull amplifierarray and a deflection coil connected to the output end of said pair oftransistors, said deflection coil being supplied with a deflectioncurrent in trace and retrace periods; b. a voltage terminal provided tobe connected to a voltage source; c. switch means connected to saidvoltage terminal; d. circuit means having charge storing means andconnected between one end of said output circuit and said switch, saidcircuit means supplying a first voltage to said output circuit andsimultaneously charging said charge storing means during the retraceperiod and supplying a second voltage lower than said first voltage tosaid output circuit by the discharging of said charge storing meansduring the trace period; and e. control means for controlling theconductivity of said switch means in response to the turning of theperiod between the trace and retrace periods.
 2. A deflection circuitaccording to claim 1, wherein said circuit means comprises a voltagesupplying path for supplying the voltage of said voltage source to saidoutput circuit, plural capacitors, first connecting means for making aseries connection of said plural capacitors connected to said voltagesupplying path to charge the series connnected plural capacitors by saidvoltage source during the retrace period and second connecting means forconnecting each of said plural capacitors to said one end of said outputcircuit with respective paths parallel to each other to make each ofsaid capacitors discharge toward said output circuit during the traceperiod.
 3. A deflection circuit according to claim 2, wherein said firstconnecting means includes at least one unidirectional element connectedbetween two of said plural capacitors, and said second connecting meansincludes plural additional unidirectional elements each connected toeach of said plural capacitors to make plural series paths connected tosaid one end of said output circuit in parallel to each other.
 4. Adeflection circuit according to claim 3, wherein said circuit meansfurther comprises an additional capacitor connected between said switchand said one end of said output circuit, an impedance element connectedto a junction between one end of said additional capacitor and saidswitch, and a further additional unidirectional element provided in saidvoltage supplying path.
 5. A deflection circuit according to claim 1,wherein said control means comprises means for supplying a controlsignal which varies in accordance with the trace and retrace periods tosaid switch means so as to make said switch means nonconductive duringthe trace period and conductive during the retrace period.
 6. Adeflection circuit according to claim 5, wherein said control meansfurther comprises means for producing said control signal in response toa pulse obtained at the output end of said couple of transistors.
 7. Adeflection circuit comprising: a. an output circuit including a pair oftransistors connected in a single-ended push-pull amplifier array and adeflection coil connected to the output end of said pair of transistors,said deflection coil being supplied with a deflection current in traceand retrace periods; b. a voltage terminAl provided to be connected to avoltage source; c. switch means with one end connected to said voltageterminal; d. circuit means comprising a connecting path connecting theother end of said switch to one end of said output circuit, a seriesconnection of a first capacitor, a first diode and a second capacitor,one end of said series connection being connected to said connectingpath, a second diode connected across the series connection of saidfirst capacitor and said first diode and a third diode connected acrossthe series connection of said first diode and said second capacitor; ande. control means for controlling the conductivity of said switch meansin response to the turning of the period between the trace and retraceperiods.
 8. A deflection circuit according to claim 7, wherein saidswitch means has a control terminal and said control means is connectedbetween said output end of said pair of transistors and said controlterminal.